Total Credits: 10
Level: Level 4
Target Students: Fourth year students on courses in Electrical and Electronic Engineering: and related courses. There is a limited number of places on this module. Students are reminded that enrolments which are not agreed by the Offering School in advance may be cancelled without notice. Available to JYA/Erasmus students.
|Autumn||Assessed by end of Autumn Semester|
Prerequisites: First and second year degree digital electronics
|H61IIC||Introduction to Electronic Engineering|
Summary of Content:
This course will be divided into two: taught material and a hands-on lab exercise.
TAUGHT MATERIAL This will contain the following:
LABORATORY EXERCISES The lab classes will be tightly integrated with the lecture sessions. The lab exercises, directly related to the lecture material will be implemented on a pre-prepared FPGA development board.
Method and Frequency of Class:
|Activity||Number Of Weeks||Number of sessions||Duration of a session|
|Lecture||3 weeks||1 per week||2 hours|
|Practical||10 weeks||1 per week||4 hours|
Method of Assessment:
|Exam 1||75||3-hour programming assignment done under examination conditions|
|Coursework 1||25||VHDL laboratory design|
Dr Y Zhu
Education Aims: To introduce students to the VHDL syntax and its latest development. The module will use the software tools from both Xilinx and Mentor Graphics to present FPGA based digital system design flow with VHDL.
By the end of the module, students should be able to
Offering School: Department of Electrical & Electronic Engineering
Use the Back facility of your browser to return to the previous page.
Search for another module
Return to The University of Nottingham Welcome Page