Catalogue of Modules, University of Nottingham

H64HPL HDL for Programmable Logic
(Last Updated:03 May 2017)

Year  17/18

Total Credits: 10

Level: Level 4

Target Students:  Fourth year students on courses in Electrical and Electronic Engineering: and related courses. There is a limited number of places on this module. Students are reminded that enrolments which are not agreed by the Offering School in advance may be cancelled without notice.  Available to JYA/Erasmus students.

Taught Semesters:

Autumn Assessed by end of Autumn Semester 

Prerequisites: First and second year degree digital electronics

H61IIC Introduction to Electronic Engineering 
H62ELD Electronic Engineering 

Corequisites:  None.

Summary of Content:  

This course will be divided into two: taught material and a hands-on lab exercise.

TAUGHT MATERIAL This will contain the following:

  • HDL overview and latest developments
  • Latest relevant software from Xilinx and Mentor Graphics
  • VHDL syntax
  • VHDL testbench design
  • Combinational and sequential circuit design
  • Finite State Machine VHDL design
  • LABORATORY EXERCISES The lab classes will be tightly integrated with the lecture sessions. The lab exercises, directly related to the lecture material will be implemented on a pre-prepared FPGA development board.

    Method and Frequency of Class:

    ActivityNumber Of WeeksNumber of sessionsDuration of a session
    Lecture 3 weeks1 per week2 hours
    Practical 10 weeks1 per week4 hours

    Activities may take place every teaching week of the Semester or only in specified weeks. It is usually specified above if an activity only takes place in some weeks of a Semester

    Further Activity Details:
    2 hours per week lectures for 3 weeks (6 hours); 10 x 4 hours (approx) lecture/lab classes (one hour for lecture and three hours for lab) (40 hours); Self-study/exam revision (54 hours).

    Method of Assessment: 

    Assessment TypeWeightRequirements
    Exam 1 75 3-hour programming assignment done under examination conditions 
    Coursework 1 25 VHDL laboratory design 

    Dr Y Zhu

    Education Aims:  To introduce students to the VHDL syntax and its latest development. The module will use the software tools from both Xilinx and Mentor Graphics to present FPGA based digital system design flow with VHDL.

    Learning Outcomes:  

    By the end of the module, students should be able to

  • Use synthesisable VHDL statements to design basic digital circuits
  • design VHDL testbench codes to simulate VHDL codes using Mentor Graphics ModelSim
  • synthesize VHDL codes and then implement them into Xilinx FPGA devices using Xilinx ISE design suite
  • Offering School:  Department of Electrical & Electronic Engineering

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